ADSP-21062KS-160

ADSP-21062KS-160, signal processing microcomputer, 2MBIT, 240MQFP, –0.3 V to +7.0 V

Rated 5 Rating 5 | reviews | Write a review

Price:: US $1.00~100.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $1.00~100.00

PartNumber:: ADSP-21062KS-160

Brand:: Analog Devices - ADI | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Jenny's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2012-05-29

From Other Seller

Part Number:ADSP-21062KS-160
US $1.00 - 100.00
EKY-160ELL121MF11D

US $0.10 - 1.00 / Piece
(0) Remove
HEF4093BT

US $0.15 - 1.20 / Piece
(0) Remove
Quantity:

piece

Product Summary

The ADSP-21062KS-160 SHARC—Super Harvard Architecture Computer—is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-21062KS-160 SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-21062KS-160 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supporte by a dedicated I/O bus.

Parametrics

ADSP-21062KS-160 maximum ratings: (1)Supply Voltage (VDD): –0.3 V to +7.0 V; (2)Input Voltage: –0.5 V to VDD + 0.5 V; (3)Output Voltage Swing: –0.5 V to VDD + 0.5 V; (4)Load Capacitance: 200 pF; (5)Storage Temperature Range: –65℃ to +150℃; (6)Lead Temperature (5 seconds): 280℃; (7)Junction Temperature Under Bias: 130℃.

Features

ADSP-21062KS-160 features: (1)Computation units (ALU, multiplier and shifter) with a shared data register file; (2)Data address generators (DAG1, DAG2); (3)Program sequencer with instruction cache; (4)PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle; (5)Interval timer; (6)On-chip SRAM; (7)External port for interfacing to off-chip memory and peripherals; (8)Host port and multiprocessor Interface; (9)DMA controller.