XC2S100-5PQG208C

Product Summary

The XC2S100-5PQG208C is a member of the Spartan-II Field-Programmable Gate Array family, which gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The seven-member family offers densities ranging from 15,000 to 200,000 system gates. System performance is supported beyond 200 MHz. The XC2S100-5PQG208C features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The XC2S100-5PQG208C is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Parametrics

XC2S100-5PQG208C absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: 5V tolerant I/O(4):–0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (5)VTS, Voltage applied to 3-state output 5V tolerant I/O:–0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (6)TSTG, Storage temperature (ambient): –65 to +150℃; (7)TJ, Junction temperature:+125℃.

Features

XC2S100-5PQG208C features: (1)Second generation ASIC replacement technology; (2)SelectRAM hierarchical memory; (3)Fully PCI compliant; (4)Low-power segmented routing architecture; (5)Dedicated carry logic for highspeed arithmetic; (6)Efficient multiplier support; (7)Cascade chain for wideinput functions; (8)Abundant registers/latches with enable, set, reset; (9)Four dedicated DLLs for advanced clock control; (10)Four primary lowskew global clock distribution nets; (11)IEEE 1149.1 compatible boundary scan logic; (12)Pbfree package options; (13)Low-cost packages available in all densities; (14)Family footprint compatibility in common packages; (15)16 high-performance interface standards; (16)Zero hold time simplifies system timing; (17)Hot swap I/O (CompactPCI friendly); (18)Core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V; (19)Fully supported by powerful Xilinx ISE development system.

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